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IC-NQC
preliminary
Rev B1, Page 1/29
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
FEATURES o Resolution of up to 8,192 angle steps per sine period o Binary and decimal resolution settings, e.g. 500, 512, 1000, 1024; programmable angle hysteresis o Count-safe vector follower principle, real-time system with 70 MHz sampling rate o Conversion time of just 250 ns including amplifier settling o Direct sensor connection; selectable input gain o Input frequency of up to 250 kHz o Signal conditioning for offset, amplitude and phase o A/B quadrature signals of up to 2 MHz with adjustable minimum transition distance o Zero signal processing, adjustable in index position and width o Absolute angle output via fast serial interface (BiSS, SSI) o Permanent bidirectional memory access to parameters and OEM data by BiSS C o Period counting with up to 24 bits o Error monitoring of frequency, amplitude and configuration o Device setup from serial EEPROM or using BiSS o ESD protection and TTL-/CMOS-compatible outputs
APPLICATIONS o Interpolator IC for angle resolution from sine/cosine sensor signals o Optical encoders o MR sensor systems
PACKAGES
TSSOP20
BLOCK DIAGRAM
Copyright (c) 2010 iC-Haus
http://www.ichaus.com
IC-NQC
preliminary
Rev B1, Page 2/29
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
DESCRIPTION IC-NQC is a monolithic A/D converter which, by applying a count-safe vector follower principle, converts sine/cosine sensor signals with a selectable resolution and hysteresis into angle position data. This absolute value is output via a bidirectional, synchronous-serial I/O interface in BiSS C protocol and trails a master clock rate of up to 10 Mbit/s. Alternatively, this value can be output so that it is compatible with SSI in Gray or binary code, with or without error bits. The device also supports double transmission in SSI ring mode. Signal periods are logged quickly by a 24-bit period counter that can supplement the output data with an upstream multiturn position value. At the same time any changes in angle are converted into incremental A QUAD B signals. Here, the minimum transition distance can be stipulated and adapted to suit the system on hand (cable length, external counter). A synchronized zero index Z is generated if enabled by PZERO and NZERO. The front-end amplifiers are configured as instrumentation amplifiers, permitting sensor bridges to be directly connected without the need for external resistors. Various programmable D/A converters are available for the conditioning of sine/cosine sensor signals with regard to offset, amplitude ratio and phase errors (offset compensation by 8-bit DAC, gain ratio by 5-bit DAC, phase compensation by 6-bit DAC). The front-end gain can be set in stages graded to suit all common complementary sensor signals from approximately 20 mVpp to 1.5 Vpp and also noncomplementary sensor signals from 40 mVpp to 3 Vpp respectively. The device can be configured using two bidirectional interfaces, the EEPROM interface from a serial EEPROM with I2 C interface, or the I/O interface in BiSS C protocol. Free storage space on the EEPROM can be accessed via BiSS for the storage of additional data. After a low voltage reset, IC-NQC reads in the configuration data including the check sum (CRC) from the EEPROM and repeats the process if a CRC error is detected.
IC-NQC
preliminary
Rev B1, Page 3/29
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
CONTENTS CONTENTS . . . . . . . . . . . . . . . . . . . PACKAGES ABSOLUTE MAXIMUM RATINGS THERMAL DATA ELECTRICAL CHARACTERISTICS CHARACTERISTICS: Diagrams . . . . . . . OPERATING REQUIREMENTS: I/O Interface PARAMETER and REGISTER SIGNAL CONDITIONING CONVERTER FUNCTIONS MAXIMUM POSSIBLE CONVERTER FREQUENCY Serial data output . . . . . . . . . . . . . . . Incremental output to A, B and Z . . . . . . . INCREMENTAL SIGNALS SIGNAL MONITORING and ERROR MESSAGES 3 4 5 5 6 8 9 10 11 12 STARTUP BEHAVIOR 13 13 14 15 APPLICATION NOTES Principle input circuits . . . . . . . . . . . . . Basic circuit . . . . . . . . . . . . . . . . . . . EVALUATION BOARD DESIGN REVIEW: Function Notes 25 26 26 27 27 27 EEPROM INTERFACE Example of CRC Calculation Routine . . . . . 24 24 TEST FUNCTIONS I/O INTERFACE: BiSS C PROTOCOL Interface Parameters With BiSS C Protocol . Example Of BiSS Data Output . . . . . . . . Register Communication . . . . . . . . . . . . Internal Reset Function . . . . . . . . . . . . Short BiSS Timeout . . . . . . . . . . . . . . I/O INTERFACE: SSI Protocol Examples Of SSI Data Output ........ 18 19 19 20 20 20 20 22 23
17
IC-NQC
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Rev B1, Page 4/29
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
PACKAGES TSSOP20 (according to JEDEC Standard) PIN CONFIGURATION TSSOP20 4.4 mm, lead pitch 0.65 mm PIN FUNCTIONS No. Name Function Input Cosine + Input Cosine +5 V Supply Voltage (analog) Ground (analog) Reference Voltage Output Incremental Output A Analog signal COS+ (TMA mode) PWM signal for Offset Sine (calib.) 7B Incremental Output B Analog signal COS- (TMA mode) PWM signal for Offset Cosine (calib.) 8Z Incremental Output Z PWM signal for Phase/Ratio (calib.) 9 GND Ground 10 VDD +5 V Supply Voltage (digital) 11 SLI I/O Interface, data input* 12 MA I/O Interface, clock line 13 SLO I/O Interface, data output 14 SDA EEPROM interface, data line Analog signal SIN+ (TMA mode) 15 SCL EEPROM interface, clock line Analog signal SIN- (TMA mode) 16 NERR Error Input/Output, active low 17 PZERO Input Zero Signal + 18 NZERO Input Zero Signal 19 PSIN Input Sine + 20 NSIN Input Sine External connections linking VDDA to VDD and GND to GNDA are required. *) If only a single IC-NQC is used and no chain circuitry of multiple BiSS slaves, pin SLI can remain unwired or can be linked to ground (GND). 1 2 3 4 5 6 PCOS NCOS VDDA GNDA VREF A
IC-NQC
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13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
ABSOLUTE MAXIMUM RATINGS
These ratings do not imply permissible operating conditions; functional operation is not guaranteed. Exceeding these ratings may damage the device. Item No. Symbol Parameter Voltage at VDDA Voltage at VDD V() < VDDA + 0.3 V V() < VDD + 0.3 V Conditions Min. -0.3 -0.3 -0.3 Max. 6 6 6 V V V Unit
G001 VDDA G002 VDD G003 Vpin()
Voltage at PSIN, NSIN, PCOS, NCOS, PZERO, NZERO, VREF, NERR, SCL, SDA, MA, SLI, SLO, A, B, Z G004 Imx(VDDA) Current in VDDA G005 Imx(GNDA) Current in GNDA G006 Imx(VDD) G008 Imx() Current in VDD Current in PSIN, NSIN, PCOS, NCOS, PZERO, NZERO, VREF, NERR, SCL, SDA, MA, SLI, SLO, A, B, Z Pulse Current in all pins (Latch-up Strength) G007 Imx(GND) Current in GND
-50 -50 -50 -50 -10
50 50 50 50 10
mA mA mA mA mA
G009 Ilu()
according to Jedec Standard No. 78; Ta = 25 C, pulse duration to 10 ms, VDDA = VDDAmax , VDD = VDDmax , Vlu() = (-0.5...+1.5) x Vpin()max HBM 100 pF discharged through 1.5 k
-100
100
mA
G010 Vd() G011 Tj G012 Ts
ESD Susceptibility at all pins Junction Temperature Storage Temperature Range
2 -40 -40 150 150
kV C C
THERMAL DATA
Operating Conditions: VDDA = VDD = 5 V 10 % Item No. T01 Symbol Ta Parameter Operating Ambient Temperature Range (extended temperature range of -40 to 125 C available on request) Conditions Min. -25 Typ. Max. 85 C Unit
All voltages are referenced to ground unless otherwise stated. All currents flowing into the device pins are positive; all currents flowing out of the device pins are negative.
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13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
ELECTRICAL CHARACTERISTICS
Operating Conditions: VDDA = VDD = 5 V 10 %, Tj = -40 ... 125 C, unless otherwise stated. Item No. Symbol Parameter Conditions Min. Typ. Max. Unit
Total Device Functionality and parameters beyond the operating conditions (with reference to independent voltage supplies, for instance) are to be verified within the individual application using FMEA methods. 001 002 003 004 005 006 VDDA, VDD I(VDDA) I(VDD) Von Vhys Vc()hi Permissible Supply Voltage Supply Current in VDDA Supply Current in VDD Turn-on Threshold VDDA, VDD Turn-on Threshold Hysteresis Clamp Voltage hi at PSIN, NSIN, PCOS, NCOS, PZERO, NZERO, VREF Vc()hi = V() - VDDA; I() = 1 mA, other pins open fin() = 200 kHz; A, B, Z open fin() = 200 kHz; A, B, Z open 3.2 200 0.3 1.6 4.5 5.5 15 20 4.4 V mA mA V mV V
007
Vc()lo
Clamp Voltage lo at I() = -1 mA, other pins open PSIN, NSIN, PCOS, NCOS, PZERO, NZERO, VREF, NERR, SCL, SDA, MA, SLI, SLO, A, B, Z Clamp Voltage hi at NERR, SCL, SDA, MA, SLI, SLO, A, B, Z Vc()hi = V() - VDD; I() = 1 mA, other pins open
-1.6
-0.3
V
008
Vc()hi
0.3
1.6
V
Input Amplifiers and Signal Inputs PSIN, NSIN, PCOS, NCOS 101 Vos() Input Offset Voltage Vin() and G() in accordance with table GAIN; G 20 G < 20 102 103 104 105 106 107 TCos Iin() GA GArel fhc SR Input Offset Voltage Temperature Drift Input Current Gain Accuracy Gain SIN/COS Ratio Accuracy Cut-off Frequency Slew Rate see 101 V() = 0 V ... VDDA G() in accordance with table GAIN G() in accordance with table GAIN G = 80 G = 2.667 G = 80 G = 2.667
-10 -15 10 -50 95 97 230 650 4 9 -1.0 -0.5 -10 0.35
10 15
mV mV V/K
50 102 103
nA % % kHz kHz V/s V/s
Sine-To-Digital Conversion 201 202 203 AAabs AAabs AArel Absolute Angle Accuracy without referred to 360 input signal, G = 2.667, calibration Vin = 1.5 Vpp, HYS = 0 Absolute Angle Accuracy after calibration Relative Angle Accuracy referred to 360 input signal, HYS = 0, internal signal amplitude of 2 ... 4 Vpp referred to signal periods at A, resp. B (see Fig. 1); G = 2.667, Vin = 1.5 Vpp, SELRES = 1024, FCTR = 0x0004 ... 0x00FF, fin < finmax (see table 16) I(VREF) = -1 mA ... +1 mA 1.0 +0.5 10 DEG DEG %
Reference Voltage Output VREF 801 VREF Reference Voltage 48 52 % VDDA MHz
Oscillator A01 fosc()max A02 fosc()
Permissible Max. Oscillator Frequency Oscillator Frequency
presented at pin SCL with subdivision of 2048; presented at pin SCL with subdivision of 2048; VDDA = VDD = 5 V 10 %, CFGOSC = 0x00 VDDA = VDD = 5 V, CFGOSC = 0x00 VDDA = VDD = 5 V, CFGOSC = 0x03 VDDA = VDD = 5 V, CFGOSC = 0x05 VDDA = VDD = 5 V
90
52 60
72 54 84 -0.1
90 83
MHz MHz MHz MHz %/K
A03
TCosc
Oscillator Frequency Temperature Drift
IC-NQC
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13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
ELECTRICAL CHARACTERISTICS
Operating Conditions: VDDA = VDD = 5 V 10 %, Tj = -40 ... 125 C, unless otherwise stated. Item No. A04 Symbol VCosc Parameter Conditions Min. Oscillator Frequency Power Sup- CFGOSC = 0x00 ply Dependance Input Offset Voltage Input Current Common-Mode Input Voltage Range Differential Input Voltage Range Saturation Voltage hi Saturation Voltage lo Rise Time Fall Time Permissible Load at A, B Threshold Voltage hi Threshold Voltage lo Hysteresis Pull-up Current in MA Pull-down Current in SLI Vt()hys = Vt()hi - Vt()lo V() = 0 ... VDD - 1 V V() = 1 ... VDD 0.8 300 -240 20 -120 120 -25 300 4 10 10 0 with read access to EEPROM powering up with no EEPROM CFGOSC = 0x00, TIMO = 0, TOA =0 1 20 2 0.8 Vt()hys = Vt()hi - Vt()lo 300 5 7 2 20 I() = 4 mA V() = 0 ... VDD - 1 V CL() = 50 pF 10 60.7 -600 -300 100 0.45 -75 60 2 1.5 50 Vs()hi = VDD - V(); I() = -4 mA I() = 4 mA CL() = 50 pF CL() = 50 pF TMA = 1 (calibration mode) 1 2 V() = Vcm() V() = 0 V ... VDDA -20 -50 1.4 0 Typ. +9 Max. %/V Unit
Zero Signal Enable Inputs PZERO, NZERO B01 B02 B03 B04 Vos() Iin() Vcm() Vdm() 20 50 VDDA1.5 VDDA 0.4 0.4 60 60 mV nA V V V V ns ns M V V mV A A MHz MHz ns s ms ms s V V mV ms V kHz V A ns ms ms
Incremental Outputs A, B, Z and I/O Interface Output SLO D01 Vs()hi D02 Vs()lo D03 tr() D04 tf() D05 RL() E01 E02 E03 E04 E05 E06 E07 E08 E09 E10 E11 F01 F02 F03 F04 F05 Vt()hi Vt()lo Vt()hys Ipu(MA) Ipd(SLI) fclk(MA) tp(MASLO) tbusy_s tbusy_r tidle t_tos Vt()hi Vt()lo Vt()hys tbusy()cfg Vt()hi
I/O Interface Inputs MA, SLI
Permissible MA Clock Frequency SSI protocol BiSS protocol Propagation Delay: MA edge vs. SLO output Processing Time Single-Cycle Data (delay of start bit) Processing Time Register Access (delay of start bit) Interface Blocking Time Timeout Threshold Voltage hi Threshold Voltage lo Hysteresis Threshold Voltage hi Write/Read Clock at SCL Saturation Voltage lo Pull-up Current Fall Time Duration of Startup Configuration error free EEPROM access RL(SLO) 1 k
EEPROM Interface Inputs SDA and Error Input NERR
EEPROM Interface Outputs SDA, SCL and Error Output NERR G01 f() G02 Vs()lo G03 Ipu() G04 ft() G05 tmin()lo G06 Tpwm() G07 t()lo
Min. Duration Of Error Indication MA = hi, no BiSS access, amplitude or frequeny at NERR (lo signal) error Cycle Duration Of Error Indication at NERR fosc() subdivided 222
Duty Cycle Of Error Indication at signal duration low to high; AERR = 0 (amplitude error) NERR FERR = 0 (frequency error) Permissible Load at SDA, SCL TMA = 1 (calibration mode) 1
75 50
% % M
G08 RL()
IC-NQC
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13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
CHARACTERISTICS: Diagrams
tAB
tMTD
B A
twhi AArel T
Figure 1: Definition of relative angle error and minimum transition distance
AArel
0.15 0.1 0.05 0 -0.05 -0.1 -0.15
0
90
180
270
360
Figure 2: Typical residual absolute angle error after calibration.
IC-NQC
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13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
OPERATING REQUIREMENTS: I/O Interface
Operating Conditions: VDD = 5 V 10 %, Ta = -25 ... 85 C; input levels lo = 0 ... 0.45 V, hi = 2.4 V ... VDD Item No. Symbol Parameter Conditions Fig. Min. Permissible Clock Period Clock Signal Hi Level Duration Clock Signal Lo Level Duration Permissible Clock Period Clock Signal Hi Level Duration Clock Signal Lo Level Duration ttos according to Table 35 ttos according to Table 45 4 4 4 5 5 5 250 25 25 100 25 25 Max. 2x ttos ttos ttos 2x ttos ttos ttos ns ns ns ns ns ns Unit
SSI Protocol I001 TMAS I002 tMASh I003 tMASl BiSS C Protocol I004 TMAS I005 tMASh I006 tMASl
Figure 3: Timing diagram in SSI protocol.
Figure 4: Timing diagram in BiSS C protocol.
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13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
PARAMETER and REGISTER Register Description, Overview . . . . . . . . . . . Page 10 Signal Conditioning . . . . . . . . . . . . . . . . . . . . . . . Page 11 GAIN: Gain Select SINOFFS: Offset Calibration Sine COSOFFS: Offset Calibration Cosine REFOFFS: Offset Calibration Reference RATIO: Amplitude Calibration PHASE: Phase Calibration Converter Function . . . . . . . . . . . . . . . . . . . . . . . . Page 12 SELRES: Resolution HYS: Hysteresis CFGOSC: Oscillator Calibration FCTR: Max. Permissible Converter Frequency Incremental Signals . . . . . . . . . . . . . . . . . . . . . . . Page 15 CFGABZ: Output A, B, Z ROT: Direction of Rotation CBZ: 24-bit Period Counter Configuration ENRESDEL: Output Delay A, B, Z ZPOS: Zero Signal Position CFGZ: Zero Signal Length CFGAB: Zero Signal Logic OVERVIEW Adr
0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F EEPROM 0x10 0x1F 0x41 0x7F 0x00 - 0x0F 0x31 - 0x6F Reserved EEPROM memory section: IC-NQC device configuration data. Reserved EEPROM memory section: BiSS C Slave Registers (device identifier 4E 51 43 33 00 00 69 43) CRC_E2P(7:0) - check value read from the EEPROM for addresses 0x00 to 0x0E reserved reserved PHASE(5:0) reserved reserved reserved SELAMPL GAIN(3:0) SINOFFS(7:0) COSOFFS(7:0) REFOFFS RATIO(4) AMPL(1:0) GRAY TIMO TOA ENRESDEL CRC6
Signal Monitoring and Error Messages . . . . . . . . . . . . . . . . . . . . . . . Page 17 SELAMPL: Amplitude Monitoring, function AMPL: Amplitude Monitoring, thresholds AERR: Amplitude Error FERR: Frequency Error Test Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 18 TMODE: Test Mode TMA: Analog Test Mode BiSS Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 19 SELSSI: Protocol Version TIMO, TOA: Timeout TOS: Timeout Short M2S: Data Output and Options CRC6: CRC Polynomial NZB: Zero Bit ENCDS: Protocol Options RPL: Register Protection Settings GRAY: SSI Data Format
Bit 7
ENCDS
Bit 6
M2S(1:0) HYS(2:0) SELSSI NZB
Bit 5
Bit 4
Bit 3
Bit 2
SELRES(4:0) ZPOS(4:0)
Bit 1
Bit 0
ROT
CBZ FCTR(7:0)
CFGABZ(1:0) RPL FCTR(14:8) TMODE(2:0) 0
CFGZ(1:0) AERR FERR
CFGAB(1:0)
TMA CFGOSC(2:0)
RATIO(3:0)
When no register protection is active, all registers permit read and write access (see RPL). Register contents are random when powering up without an EERPOM.
Table 5: Register layout
IC-NQC
preliminary
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13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
SIGNAL CONDITIONING Input stages SIN and COS are configured as instrumentation amplifiers. The amplifier gain must be selected in accordance with the input signal amplitude and programmed to register GAIN according to the folGAIN Adr 0x08, Bit 7:4 Sine/Cosine Input Signal Levels Vin() Amplitude Average value (DC) Single-ended Differential Single-ended up to 100 mVpp 0.7 V ... VDDA - 1.2 V 0.8 V ... VDDA - 1.2 V up to 120 mVpp 0.7 V ... VDDA - 1.2 V 0.8 V ... VDDA - 1.2 V up to 0.15 Vpp 0.7 V ... VDDA - 1.2 V 0.8 V ... VDDA - 1.2 V up to 0.2 Vpp 1.2 V ... VDDA - 1.2 V 1.3 V ... VDDA - 1.3 V up to 0.24 Vpp 1.2 V ... VDDA - 1.2 V 1.3 V ... VDDA - 1.3 V up to 0.28 Vpp 0.7 V ... VDDA - 1.2 V 0.8 V ... VDDA - 1.3 V up to 0.3 Vpp 1.2 V ... VDDA - 1.2 V 1.3 V ... VDDA - 1.3 V up to 0.4 Vpp 0.7 V ... VDDA - 1.2 V 0.8 V ... VDDA - 1.3 V up to 0.56 Vpp 1.2 V ... VDDA - 1.3 V 1.4 V ... VDDA - 1.4 V up to 0.8 Vpp 1.2 V ... VDDA - 1.3 V 1.4 V ... VDDA - 1.5 V up to 1 Vpp 0.8 V ... VDDA - 1.4 V 1.0 V ... VDDA - 1.6 V up to 1.2 Vpp 0.8 V ... VDDA - 1.4 V 1.1 V ... VDDA - 1.7 V up to 1.5 Vpp 0.9 V ... VDDA - 1.5 V 1.3 V ... VDDA - 1.9 V up to 2 Vpp 1.2 V ... VDDA - 1.6 V 1.7 V ... VDDA - 2.1 V up to 2.4 Vpp 1.2 V ... VDDA - 1.7 V 1.8 V ... VDDA - 2.3 V up to 3 Vpp 1.3 V ... VDDA - 1.8 V 2.0 V ... VDDA - 2.6 V
lowing table. Half of the supply voltage is available at VREF as a center voltage to enable the DC level to be adapted.
Code 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00
Amplification 80.000 66.667 53.333 40.000 33.333 28.571 26.667 20.000 14.287 10.000 8.000 6.667 5.333 4.000 3.333 2.667
Differential up to 50 mVpp up to 60 mVpp up to 75 mVpp up to 0.1 Vpp up to 0.12 Vpp up to 0.14 Vpp up to 0.15 Vpp up to 0.2 Vpp up to 0.28 Vpp up to 0.4 Vpp up to 0.5 Vpp up to 0.6 Vpp up to 0.75 Vpp up to 1 Vpp up to 1.2 Vpp up to 1.5 Vpp
Table 6: Input gain
SINOFFS COSOFFS Code 0x00 0x01 ... 0x7F 0x80 0x81 ... 0xFF Notes Adr 0x09, Bit 7:0 Adr 0x0A, Bit 7:0 Output Offset 0V -7.8125 mV ... -0.9922 V 0V +7,8125 mV ... +0.9922 V RATIO Code Input Offset 0V -7.8125* mV / GAIN ... -0.9922 V / GAIN 0V +7.8125 mV / GAIN ... +0.9922 V / GAIN 0x00 0x01 ... 0x0F Adr 0x0B, Bit 0, Adr 0x08, Bit 3:0 COS / SIN Code COS / SIN 1.0000 1.0067 ... 1.1 0x10 0x11 ... 0x1F 1.0000 0.9933 ... 0.9000
Table 9: Amplitude calibration
PHASE Code 0x00 0x01 ... 0x12 ... 0x1F Adr 0x0B, Bit 7:2 Phase Shift 90 90.703125 ... 102.65625 102.65625 102.65625
Code 0x20 0x21 ... 0x32 ... 0x3F
Phase Shift 90 89.296875 ... 77.34375 77.34375 77.34375
*) With REFOFFS = 0x00 and VDDA = 5 V.
Table 7: Sine/cosine offset calibration
REFOFFS Code 0x00 0x01 Adr 0x0B, Bit 1 Reference Voltage Dependent on VDDA (example of application: MR sensors) Not dependent on VDDA (example of application: Sin/Cos encoders)
Table 10: Phase calibration
Table 8: Offset reference
IC-NQC
preliminary
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13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
CONVERTER FUNCTIONS
SELRES Code Adr 0x00, Bit 4:0 Binary Examples of Permissible Resolutions Input Frequencies finmax (FCTR 0x0004, 0x4302) 8192 4096 2048 1024 512 256 128 64 32 16 8 SELRES Code Adr 0x00, Bit 4:0 Decimal Examples of Permissible Resolutions Input Frequencies finmax (FCTR 0x0004, 0x4302) 2000 1600 1000 800 500 400 250 *1 125 *1,2 320 160 *2 80 *4 40 *8 200 100 *2 50 *1,4 25 *1,8
*1 *2,4,8
0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F
158 Hz, 1.06 kHz 317 Hz, 2.12 kHz 634 Hz, 4.24 kHz 1.27 kHz, 8.5 kHz 2.54 kHz, 17 kHz 5.1 kHz, 34 kHz 10.2 kHz, 68 kHz 20.3 kHz, 136 kHz 40.6 kHz (max. 250 kHz) 81.3 kHz (max. 250 kHz) 162 kHz (max. 250 kHz)
0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F Notes
650 Hz, 4.3 kHz 812 Hz, 5.5 kHz 1.3 kHz, 8.6 kHz 1.6 kHz, 10.8 kHz 2.6 kHz, 17 kHz 3.2 kHz, 22 kHz 5.2 kHz, 35 kHz 5.2 kHz, 35 kHz 4.1 kHz, 27 kHz 4.1 kHz, 27 kHz 4.1 kHz, 27 kHz 4.1 kHz, 27 kHz 6.5 kHz, 43.3 kHz 6.5 kHz, 43.3 kHz 6.5 kHz, 43.3 kHz 6.5 kHz, 43.3 kHz
Table 11: Binary resolutions
Not suitable for incremental output on A, B. The internal resolution is higher by a factor of 2, 4 or 8.
Table 12: Decimal resolutions
HYS Code 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 Adr 0x01, Bit 7:5 Hysteresis in Hysteresis in degrees LSB 0 0.0879 0.1758 0.3516 0.7031 1.4063 5.625 45 1 LSB @ 12 bit 1/2 LSB @ 10 bit 1 LSB @ 10 bit 1/2 LSB @ 8 bit 1 LSB @ 8 bit only recommended for calibration 0.044 0.088 0.176 0.352 0.703 2.813 22.5 Absolute error* CFGOSC Code 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 Adr 0x07, Bit 2:0 Trimming Frequency No change -10 % -14.4 % -22 % Not permissible +12.5 % +6.25 % -4.5 %
Table 14: Oscillator calibration
Notes
*) The resulting absolute error is equivalent to half the angle hysteresis.
Table 13: Hysteresis
IC-NQC
preliminary
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13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
MAXIMUM POSSIBLE CONVERTER FREQUENCY The converter frequency automatically adjusts to the value required by the input frequency and resolution. This value ranges from zero to a maximum dependent on the oscillator frequency that is set via register FCTR. Serial data output For BiSS or SSI output the maximum possible converter frequency can be adjusted to suit the maximum input frequency; an automatic converter resolution step-down feature can be enabled via the FCTR register. Should the input frequency exceed the frequency limit of the selected converter resolution, the LSB is kept stable and not resolved any further; the interpolation resolution halves. If the next frequency limit is overshot, the LSB and LSB +1 are kept stable and so on. If the input frequency again sinks below this frequency threshold, fine resolution automatically returns. With the programming of CRC6 = 1 a resolution stepdown will be signalled via the BiSS warning bit.
Max. Possible Converter Frequency For Serial Data Output Resolution Protocol Max. Input Frequency Restrictions Requirements at high input frequency FCTR Min. Res. bin dec BiSS SSI finmax 0x0004 X X X X f(OSC)min / 40 / Resolution - 0x4102 8 X X X X f(OSC)min / 24 / Resolution Rel. angle error 2x increased 0x4202 16 X X X X 2 x f(OSC)min / 24 / Res. Rel. angle error 4x increased 0x4302 32 X X X X 4 x f(OSC)min / 24 / Res. Rel. angle error 8x increased 0x4702 64 X X X 8 x f(OSC)min / 24 / Res. Resolution lowered by factor of 2 0x4B02 128 X X X 16 x f(OSC)min / 24 / Res. Res. lowered by factor of 2-4 0x4F02 256 X X X 32 x f(OSC)min / 24 / Res. Res. lowered by factor of 2-8 0x5302 512 X X X 64 x f(OSC)min / 24 / Res. Res. lowered by factor of 2-16 0x5702 1024 X X X 128 x f(OSC)min / 24 / Res. Res. lowered by factor of 2-32 0x5B02 2048 X X X 256 x f(OSC)min / 24 / Res. Res. lowered by factor of 2-64 0x5F02 4096 X X X 512 x f(OSC)min / 24 / Res. Res. lowered by factor of 2-128 0x6302 8192 X X X 1024 x f(OSC)min / 24 / Res. Res. lowered by factor of 2-256 Notes *) Calculated with fosc()min taken from Electrical Characteristics, item A01.
Examples* finmax [kHz] at resol. 8192 1024 200 0.16 1.27 6.5 0.26 2.1 10.8 0.53 4.2 21.6 1.06 8.5 43.3 2.1 16.9 4.2 33.8 8.5 67.7 16.9 135 33.8 250 67.7 135 250 -
Table 15: Maximum converter frequency for serial data output.
IC-NQC
preliminary
Rev B1, Page 14/29
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
Incremental output to A, B and Z Settings for the maximum possible converter frequency using register FCTR are governed by two criteria: 1. The maximum input frequency 2. System restrictions caused by slow counters or data transmission via cable
also make a suitable zero-delay digital glitch filter that acts on ESD impact on the sensor and keeps the output signals spike free through temporal separation, for example. Serial data output is possible at any time in BiSS or SSI protocol. However, for the transfer of angle data to the output register the incremental output is halted for one period of the clock signal at pin MA.
In this case it is sensible to preselect a minimum transition distance for the output signals. These settings
1. Max. Possible Converter Frequency Defined By The Maximum Input Frequency Output Frequency Resolution Maximum Input Frequency Restrictions fout @ finmax Requirem. at high input frequency FCTR A, B bin dec finmax 0x0004 325 kHz X X f(OCS)min / 40 / Resolution None 0x4102 542 kHz X X f(OSC)min / 24 / Resolution Relative angle error 2x increased 0x4202 1.08 MHz X X 2 x f(OSC)min / 24 / Res. Relative angle error 4x increased 0x4302 2.17 MHz X X 4 x f(OSC)min / 24 / Res. Relative angle error 8x increased Notes *) Calculated with fosc()min taken from Electrical Characteristics, item A01. Examples* finmax [kHz] at resol. 8192 1024 200 0.16 1.27 6.5 0.26 2.1 10.8 0.53 4.2 21.6 1.06 8.5 43.3
Table 16: Maximum possible converter frequency for incremental A/B/Z output, defined by the maximum input frequency
2. Max. Possible Converter Frequency Defined By The Minimum Transition Distance Output Frequency Resolution Minimum Transition Distance Restrictions Example* fout @ tMTD Requirem. at A, B at high input frequency tMTD [sec] FCTR A, B bin dec tMTD 0x00FF 11 kHz X X 2048 / f(OSC)max None 22.8 0x00FE 11.03 kHz X X 2040 / f(OSC)max None 22.7 0x00FD 11.07 kHz X X 2032 / f(OSC)max None 22.6 ... ... ... ... ... ... ... 0x0006 402 kHz X X 56 / f(OSC)max None 0.62 0x0005 536 kHz X X 48 / f(OSC)max None 0.53 0x0004 562 kHz X X 40 / f(OSC)max None 0.44 0x4102 938 kHz X X 24 / f(OSC)max Relative angle error 2x increased 0.27 0x4202 1.87 MHz X X 12 / f(OSC)max Relative angle error 4x increased 0.13 0x4302 3.75 MHz X X 6 / f(OSC)max Relative angle error 8x increased 0.07 Notes *) Calculated with fosc()max taken from El.Char., item A01; transition distance output A vs. output B with same direction of rotation.
Table 17: Maximum possible converter frequency for incremental A/B/Z output, defined by the minimum transition distance
IC-NQC
preliminary
Rev B1, Page 15/29
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
INCREMENTAL SIGNALS
CFGABZ Code 0x00 0x01 0x02
Adr 0x02, Bit 3:2 Mode Normal Control signals for external period counters Calibration mode Offset+Phase The following settings are required additionally: SELRES = 0x0D ZPOS = 0x00 HYS = 0x07 ROT = 0x00 CFGAB = 0x00 AERR = 0x00 Calibration mode Offset+Amplitude The following settings are required additionally: SELRES = 0x0D ZPOS = 0x00 HYS = 0x07 ROT = 0x00 CFGAB = 0x00 AERR = 0x00
A A CA
B B CB
Z Z CZ
Figure 5: Offset SIN*
Figure 6: Offs. COS*
Figure 7: Phase*
0x03
Figure 8: Offset SIN*
Figure 9: Offs. COS*
Figure 10: Amplit.*
Notes
*) Trimmed accurately when duty cycle is 50 %; Recommended trimming order (after selecting GAIN): offset, phase, amplitude ratio, offset;
Table 18: Outputs A, B, Z
ROT Code 0x00 0x01 Adr 0x02, Bit 5 Code direction Ascending order, B then A Descending order, A then B
SIN
Table 19: Code direction
COS
cw: F->0
CBZ Code 0x00 0x01
Adr 0x02, Bit 4 Reset via zero Not activated Activated
FFFFFF
000000 ccw: 0->F
P(23:0)
A B Z
Table 20: Reset enable for period counter
-180
-90
0
45
90
180
ENRESDEL
Code 0x00 0x01
Adr 0x02, Bit 7 Output* Function immediately after 5 ms An external counter displays the absolute angle following power-on. An external counter only displays changes vs. the initial power-on (conditional on standby at power-on)
Figure 11: Period counter reset by zero signal (enabled by CBZ = 1). Example gives a resolution of 64 (SELRES = 0x0A), a zero signal at 45 (ZPOS = 0x04, CFGAB = 0x00) and no inversion of the direction of rotation (ROT = 0x00, COS leads SIN).
Notes
*) Output delay after device configuration and internal reset.
Table 21: Output delay A, B, Z
IC-NQC
preliminary
Rev B1, Page 16/29
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
ZPOS Code 0x00 0x08 0x10 0x18 0x01 ... 0x1F Notes
Adr 0x01, Bit 4:0 Position 0 90 180 270 11.25 (1 x 11.25) ... 348.75 (31 x 11.25) The zero signal is only output if released by the input pins (for instance with PZERO = 5 V, NZERO = VREF).
CFGZ Code 0x00 0x01 0x02.. 03
Adr 0x02, Bit 1:0 Length 90 180 Synchronization
Table 23: Zero signal length
CFGAB Code 0x00 0x01 0x02 0x03 Adr 0x03, Bit 5:4 Z = 1 for B = 1, A = 1 B = 0, A = 1 B = 1, A = 0 B = 0, A = 0
Table 22: Zero signal position
Table 24: Zero signal logic
SIN
COS
A B Z (CFGZ= 0) Z (CFGZ= 1) Z (CFGZ= 2) -180 -90 0 45 90 180 Winkel
Figure 12: Incremental output signals for various zero signal lengths. Example gives a resolution of 64 (SELRES = 0x0A), a zero signal position of 45 (ZPOS = 0x04, CFGAB = 0x00) and no inversion of the direction of rotation (ROT = 0x00, COS leads SIN).
IC-NQC
preliminary
Rev B1, Page 17/29
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
SIGNAL MONITORING and ERROR MESSAGES
SELAMPL AMPL Code 0x00 0x01 0x02 0x03 Code 0x04 0x05 0x06 0x07 Notes Adr 0x0C, Bit 2 Adr 0x0C, Bit 1:0 Max ( |Sin| , |Cos| ) Voltage threshold Vth 0.60 x VDDA 0.64 x VDDA 0.68 x VDDA 0.72 x VDDA Sin2 + Cos2 Vthmin Vthmax 0.20 0.9 x VDDA 0.30 0.9 x VDDA 0.40 0.9 x VDDA 0.50 0.9 x VDDA Output amplitude* 1.0 Vpp 4.5 Vpp 1.5 Vpp 4.5 Vpp 2.0 Vpp 4.5 Vpp 2.5 Vpp 4.5 Vpp Output amplitude* 1.4 Vpp 2.0 Vpp 2.6 Vpp 3.1 Vpp
Vss Vth
Figure 13: Signal monitoring at minimum amplitude.
Vthmax Vthmin
*) Entries are calculated with VDDA = 5 V.
Table 25: Signal amplitude monitoring
Figure 14: Sin2 + Cos2 signal monitoring.
AERR Code 0x00 0x01
Adr 0x03, Bit 1 Amplitude error message disabled enabled Error Messages Failure Mode
Table 26: Amplitude error
No error Amplitude error Frequency error System error* Warning** Notes *System error **Warning Line Signal SLO
Error bits E1, E0 for BiSS and SSI CRC6 = 0 1, 1 0, 1 1, 0 0, 0 --
Error bits nE, nW for BiSS and SSI CRC6 = 1 1, nW 0, nW 0, nW 0, nW nE, 0
FERR Code 0x00 0x01 Notes
Adr 0x03, Bit 0 Excessive frequency error message disabled enabled Input frequency monitoring is operational for resolutions 16
NERR pulled low by external signal Automatic step-back of resolution Data output is deactivated and SLO permanently high in case of: configuration phase, invalid configuration, undervoltage.
Table 27: Frequency error
Configuration error Always enabled
Table 30: Error messages To enable the diagnosis of faults, the various types of error are signaled at NERR using a PWM code as given in the key on the left. Two error bits are provided to enable communication via the I/O interface; these bits can decode four different types of error. If NERR is held at low by an external source, such as an error message from the system, for example, this can also be verified via the I/O interface. Error are stored until the sensor data is output via the I/O interface and then deleted. Errors at NERR are displayed for a minimum of ca. 10 ms unless they are deleted beforehand by a data output.
Table 28: Configuration error
Error Indication at NERR Failure Mode No error Amplitude error Frequency error Configuration Undervoltage System error Pin signal NERR HI LO/HI = 75 % (resp. HI for AERR = 0) LO/HI = 50 % (resp. HI for FERR = 0) LO LO NERR = low caused by an external error signal
Table 29: Error indication at NERR
IC-NQC
preliminary
Rev B1, Page 18/29
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
If an error in amplitude occurs, conversion is terminated and the incremental output signals halted. An
error in amplitude rules out the possibility of an error in frequency.
TEST FUNCTIONS
TMODE Code 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 Condition Adr 0x06, Bit 3:1 Signal at Z Z A xor B ENCLK NLOCK CLK DIVC PZERO - NZERO TP CFGABZ = 0x00 TMA Code 0x00 0x01 Notes Adr 0x06, Bit 0 Pin A Pin B A COS+ B COS-
Description no test mode Output A EXOR B iC-Haus device test iC-Haus device test iC-Haus device test iC-Haus device test iC-Haus device test iC-Haus device test
Pin SDA SDA SIN+
Pin SCL SCL SIN-
To permit the verification of GAIN and OFFSET settings, signals are output after the input amplifier. A converter signal of 4 Vpp is the ideal here and should not be exceeded. Loads of 1 M and above are recommended for accurate measurement. EEPROM access is not possible during mode TMA.
Table 32: Analog test mode
Table 31: Test mode The signal is set to ca. 4 Vpp using GAIN and must not be altered after calibration. Both display modes are suitable for OFFS (positive values) and RATIO adjustments; X/Y mode is preferable for PHASE. Test signals COS- (pin B) and SIN- (pin SCL) must be selected to set negative values for OFFS.
5V A: COS+ SDA: Sin+
0V
Y/T 1 V/Div vert.
X/Y 1 V/Div vert. 1 V/Div hor.
Figure 15: Calibrated signals in TMA mode.
IC-NQC
preliminary
Rev B1, Page 19/29
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
I/O INTERFACE: BiSS C PROTOCOL The serial I/O interface operates in BiSS C protocol mode and enables sensor data to be output in uninterruptible cycles (data channel SCD). At the same time parameters can be exchanged via bidirectional register communication (data channel CD). The sensor data produced by IC-NQC contains the angle value (S) with 3 to 13 bits, the period count (P) with 0, 8, 12 or 24 bits, two error bits (E1 and E0) and 5 or 6 CRC bits (CRC). Interface Parameters With BiSS C Protocol
SELSSI Code 0 1
Adr 0x02, Bit 6 Protocol BiSS C SSI
Information
www.biss-interface.com
Table 34: Protocol version
TIMO Code
Adr 0x06, Bit 5 Clock Timeout ttos 46-47 5-6 Addr 0x07, Bit 3 see TIMO adaptive with TCLK = 42/fosc ca. 20 s ca. 2.5 s
fclk(MA) min* 50 kHz 400 kHz
Figure 16: Example line signals (BiSS C)
Single Cycle Data Channel: SCD Bits Typ Label 0...24 3...13 1 1 5...6 DATA DATA ERROR ERROR CRC Period counter P(23:0): 0, 8, 12, 24 bit (multiturn position) Angle data S(12:0): 3 bis 13 bit (singleturn position) Error bit E1 (amplitude error) Error bit E0 (frequency error) Polynomial 0x25 x5 + x2 + x0 (inverted bit output) - oder Polynomial 0x43 x6 + x1 + x0 (inverted bit output)
0 1 TOA 0 1
see BiSS specification
50 kHz
Notes
32 A ref. clock count is equal to fosc (see El. Char., A02). The permissible max. clock frequency is specified by E06. *) A low clock frequency can reduce the permissible maximum input frequency since conversion is paused for one MA cycle from Latch onwards.
Table 35: Timeout configuration (protectable)
Table 33: BiSS data channels
M2S Code 0x00 0x01 0x02 0x03 Adr 0x00, Bit 6:5 Data Length P(7:0) P(11:0) P(23:0)
CRC Polynomial 0x25 (with CRC6 = 0) 0x25 (with CRC6 = 0) 0x43 0x43
Table 36: Period counter output
CRC6 Code 0 1
Adr 0x03, Bit 7 CRC Polynomial determined by M2S 0x43
Status Messages E1, E0 nE, nW
Table 37: CRC polynomial
IC-NQC
preliminary
Rev B1, Page 20/29
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
NZB Code 0 1 Notes
Adr 0x03, Bit 6 Function Zero bit No zero bit The optional zero bit is output as the final bit after the CRC.
SCD: Angle data with 8-bit period count Bits Type Label 8 13 2 5 1 Config. DATA DATA ERROR CRC Zero Period counter P(7:0) Angle data S(12:0) Error bits E1, E0 Polynomial 0x25 Zero bit
Table 38: Zero bit
SELRES = 0x03, M2S = 0x01, CRC6 = 0, NZB = 0
Table 41: Example format 2
ENCDS Code 0x00 0x01 Adr 0x00, Bit 7 Description Data output BiSS B or SSI Data output BiSS C SCD: Angle data with 24-bit period count Bits Type Label 24 13 2 6 Config. DATA DATA ERROR CRC Period counter P(23:0) Angle data S(12:0) Error bits E1, E0 Polynomial 0x43 (no zero bit)
Table 39: Protocol options
SELRES = 0x03, M2S = 0x03, CRC6 = 0, NZB = 1
M2S can be used to set the number of period counter bits sent as sensor data. The counter bits are transmitted before the angle value, with the MSB leading.
Table 42: Example format 3 Register Communication After the BiSS C protocol slave registers are directly addressed in a reserved address area (0x40 to 0x7F). Other storage areas are addressed dynamically and in blocks. BiSS addresses 0x00 to 0x3F aim for a register bank consisting of 64 bytes, the physical storage address of which is determined by Bank Select n. IC-NQC supports up to 16 storage banks, making it possible to use an 8-bit EEPROM to its full capacity. There is therefore also enough storage space for an ID plate (EDS) and OEM data. Information regarding memory map and addressing via BiSS is given on page 25). Internal Reset Function A write access at RAM address 0x00 (BiSS address 0x00 with Bank Select n = 0) triggers an internal reset. Based on the current configuration in the RAM, iCNQC restarts without reading the EEPROM. The configured interface timeout and write protect settings become active, the period counter is set to zero and any stored configuration errors are deleted. Providing no amplitude error is present, the converter again counts up from an angle value of zero to the current angle position. Short BiSS Timeout For programming via the I/O interface IC-NQC has a short BiSS timeout function according to the description of the BiSS C protocol (see page 19, Table 2, El. Char. no. 6).
The 5-bit CRC output is based on polynomial 0x25 (100101b), with the 6-bit CRC output based on polynomial 0x43 (1000011b) automatically coming active with longer SCD data, or when preselected by CRC6. As a rule, CRC bits are sent inverted.
An additional zero bit can be output following the CRC bits. However, disabling the zero bit by NZB = 1 is recommended when the output data length does not need to comply with existing applications.
To obtain a position data output being compatible to the BiSS B protocol parameter ENCDS = 0 does switch off the CDS bit, without a replacement by a zero bit. Thus, the output data length is shorten by one bit and register communication is limited to the direction of the master to the slave. The bidirectional BiSS C register communication must be enabled by setting ENCDS = 1.
Example Of BiSS Data Output
SCD: Angle data Bits Typ 12 2 6 Config. DATA ERROR CRC
Label Angle data S(11:0) Error nE and warning nW Polynomial 0x43
SELRES = 0x04, M2S = 0x00, CRC6 = 0, NZB = 1
Table 40: Example format 1 for BiSS profile BP1
IC-NQC
preliminary
Rev B1, Page 21/29
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
Regardless of register protection settings a short timeout of typically 1.8 s can be temporarily activated by writing value 0x07 to address 0x7C (address 124d). A controller can then transmit the device configuration over a shorter period.
TOS Code 000 001...111 Adr 0x7C, Bit 2:0 Function Regular timeout (configured by TIMO) Short timeout (equal to TIMO = 1)
The value written to address 0x7C is also transferred to the EEPROM, provided an EEPROM has been connected up and is available. On reading address 0x7C the byte stored in the EEPROM is output as part of the BiSS device ID. Here, high-order bits 7:3 are part of the manufacturer's ID; low-order bits 2:0 act as an indicator of the timeout options (regular or short timeout, see Table 43).
Table 43: Short timeout (via BiSS device ID)
IC-NQC
preliminary
Rev B1, Page 22/29
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
I/O INTERFACE: SSI Protocol IC-NQC can transmit position data in SSI protocol mode; the parameters described in the following give the necessary settings and options.
M2S Code 0x00 0x01 0x02 0x03 Adr 0x00, Bit 6:5 Period counter output length P(7:0) P(11:0) P(23:0)
Table 46: Period counter for SSI data output
CRC6 NZB Code 00 01 10 11 Adr 0x03, Bit 7 Adr 0x03, Bit 6 Additional bits E1, E0 none E1, E0, zero bit none
Figure 17: Example line signal (SSI)
SELSSI Code 0 1 Adr 0x02, Bit 6 Protocol BiSS C SSI
Ring operation no no yes yes
Table 47: Options for SSI data output
GRAY Code 0 1 Notes Adr 0x05, Bit 7 SSI data format binary coded gray coded Data output starts with MSB for binary or Gray coded data.
Table 44: Protocol version
TIMO Code 0 1 TOA 0 1 Notes Adr 0x06, Bit 5 Timeout ttos Long: ca. 20 s not permitted Adr 0x07, Bit 3 see TOS not permitted
32 A ref. clock count is equal to fosc (see El. Char. A01). The permissible max. clock frequency is specified by item E06. *) A low clock frequency can reduce the permissible maximum input frequency since conversion is paused for one MA cycle from Latch onwards.
fclk(MA)min* 50 kHz
Table 48: SSI data format
Table 45: Timeout configuration for SSI
IC-NQC
preliminary
Rev B1, Page 23/29
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
Examples Of SSI Data Output
SSI Output Formats 13-bit SSI Res Mode Error CRC X Example 13 bit SSI
*1
T1 S9
T2 S8
T3 S7
T4... T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 S6 ... S0 E1 S2 E0 S1 0 0 S0
Stop Stop Stop Stop Stop Stop Stop Stop Stop Stop Stop Stop
10 bit SSI
0
0
0
0
0
0
0
0
0
0
0
0
Example
S12 S11 S10 S9 ... S3
Stop Stop Stop Stop Stop Stop Stop Stop Stop Stop Stop Stop
0 S12 S11 S10 S9 ... S3 S2 S1 S0
0
0
0
0
0 S8
0 S7
0 S6
0 S5
0 S4
0 S3
0 S2
SSI-R *2
Example
Stop S12 S11 S10 S9
0 S12 S11 S10 S9 ... S3 P7 P6 P5 S2 S1 S0 S8 E1 S7 E0 S6 0 0 P4 ... P0, S10 S9 S12, S11 S5
Stop Stop Stop Stop Stop Stop Stop Stop Stop
25-bit SSI 13 bit SSI 8 + 13 SSI bit*3 X X Example Example Configuration Input SLI = 0, SELSSI = 1, M2S = 0x00, CRC6 = 0, NZB = 0, unless otherwise noted. *1) CRC6 = 0, NZB = 1; *2) CRC6 = 1, NZB = 1; *3) M2S = 0x01 Caption SSI = SSI protocol SSI-R = SSI ring operation 0 S4 0 S3 0 S2 0 S1 0 S0 0 E1 0 E0 0 0 0 0
Stop
0
Table 49: SSI transmission formats
IC-NQC
preliminary
Rev B1, Page 24/29
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
EEPROM INTERFACE The serial EEPROM interface consists of the two pins SCL and SDA and enables read and write access to a serial EEPROM with I2 C interface (such as a 24C02 with 128 bytes, 5 V type with a 3.3 V function). The configuration data in the EEPROM, of addresses 0x00 to 0x0F, is secured by a CRC check value to address 0x0F. When the device is powered up, the address range from 0x00 to 0x0F is mapped onto iCNQC's configuration RAM. The higher memory area contains BiSS C slave registers and optional memory banks available to the sensor system. The register access to the configuration data and the memory banks 1 to 7 (intended for EDS) can be restricted by parameter RPL. Example of CRC Calculation Routine
unsigned char ucDataStream = 0 ; i n t iCRCPoly = 0x127 ; unsigned char ucCRC=0; int i = 0; ucCRC = 0 ; / / s t a r t v a l u e ! ! ! f o r ( iReg = 0 ; iReg <15; iReg ++) { ucDataStream = ucGetValue ( iReg ) ; f o r ( i =0; i <=7; i ++) { i f ( ( ucCRC & 0x80 ) ! = ( ucDataStream & 0x80 ) ) ucCRC = (ucCRC << 1 ) ^ iCRCPoly ; else ucCRC = (ucCRC << 1 ) ; ucDataStream = ucDataStream << 1 ; } }
Register Configuration BiSS Adr BiSS Adr hex decimal 0x00...0F 0x10...1F 0x20...3F 0...15 16...31 32...63
Contents Config. Data RAM (16 bytes) Config. Data EEPROM (16 bytes) Unused memory area (32 bytes)
BiSS C Slave-Registers (direct addresses): 0x40 64 Bank Select (1 byte) 0x41 65 EDS Bank (1 byte) 0x42...43 0x44...47 0x48...77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F 66...67 68...71 72...119 120 121 122 123 124 125 126 127 Profile ID (2 bytes) Serial No. (4 bytes) Slave Registers (48 bytes) Device ID (6 bytes): 4E (default) 51 (default) 43 (default) 31 (default) Bit 7:3: Adr 0x00, Bit 2:0: TOS 00 (default) Manufacturer's ID (2 bytes): 69 (default) 43 (default)
Table 51: Register overview
RPL Code 0x0 0x1 Notes Adr 0x03, Bit 3 Bank 0 0x40..7F Config. Dat. BiSS ID read / write read / write read*
Bank 1..7 EDS read / write read
Bank 8..15 User Data read / write read / write
CRC_E2P Code 0x00 ... 0xFF
Adr 0x0F, Bit 7:0 Description Check value formed by CRC polynomial 0x127
*) Exception: write to 0x40 and 0x7C is always possible.
Table 52: Register protection settings
Table 50: Check value for EEPROM data
IC-NQC
preliminary
Rev B1, Page 25/29
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
Figure 18: Registers and addressing
STARTUP BEHAVIOR After the supply has been turned on (power on reset), IC-NQC reads the configuration data from the EEPROM and during this phase halts error pin NERR actively on a low signal (open drain output) as well as data output SLO on a high signal. After a successful CRC the data output is released and the error indication at pin NERR reset; an external pull-up resistor can supply a high signal. IC-NQC then switches to normal operation and determines the current angle position, providing that a sensor is connected up to it and there is no amplitude error (or this is deactivated). Should the CRC prove unsuccessful due to a data error (disrupted transmission, no EEPROM or the EEPROM is not programmed), the configuration phase is automatically repeated. After a third failed attempt, the procedure is aborted and error pin NERR remains active, displaying a permanent low. After startup, IC-NQC does not recognize a defined configuration; the configuration RAM can contain any values. So that it is always possible to configure the setup using the I/O interface - even without an EEPROM - iCNQC first ignores parameters TIMO, TOA and RPL. The I/O interface can then be addressed in BiSS C protocol with the longest timeout (30 s maximum), without safety settings being observed (cf. RPL = 0x0).This allows the configuration to be written to RAM addresses 0x01 to 0x0C and to address 0x00. Address 0x00 must be written to last of all and triggers an internal reset (see description on page 20). A short timeout of 3 s maximum can be temporarily activated by writing value 0x07 to address 0x7C (address 124d) to keep the device configuration time shorter. When operated without an EEPROM, IC-NQC does not respond to higher addresses - with the exception of the BiSS addresses reserved for manufacturers and device IDs (0x78 to 0x7F). This address area supplies the chip version from the ROM.
IC-NQC
preliminary
Rev B1, Page 26/29
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
APPLICATION NOTES Principle input circuits
PSIN + 11App + PSIN RS1 25kS NSIN RS2 25kS NSIN + INPUT SIN VREF RS 120S NSIN NSIN + INPUT SIN VREF -
PSIN
-
1Vss to 120S PSIN
-
SENSOR
case
IC-NQC
SENSOR
case
IC-NQC
Figure 20: Input circuit for current signals of 11 A with no ground reference. Offset calibration is not possible with this circuit.
Figure 19: Input circuit for voltage signals of 1 Vpp with no ground reference. When ground is not separated the connection NSIN to VREF must be omitted.
R3 1kS R1 1kS R2 1kS V-GEN 1Vpp + R4 1kS PSIN +
+5V R001 1kS R002 1kS -
PSIN +
NSIN + INPUT SIN VREF
V-GEN 2Vpp NSIN
-
+ INPUT SIN VREF
IC-NQC
Figure 21: Input circuit for non-symmetrical voltage or current source signals with ground reference (adaptation via resistors R3, R4).
R1 10kS
IC-NQC
Figure 22: Simplified input wiring for nonsymmetrical voltage signals with ground reference.
+TTL -TTL or open 5kS 5kS RS3 1kS PSIN +
-
PSIN +
+SIN
+ R2 10kS
120S -SIN
RS1 5kS RS2 5kS
CS1 220pF RS4 1kS NSIN +
GAIN= 10
Ip 10App
In 10App NSIN
-
INPUT SIN
+ INPUT SIN VREF
ENCODER
VREF case CS2 47nF
IC-NQC
IC-NQC
Figure 23: Input circuit for complementary low-side current source outputs, such as for optoencoder iC-WG.
Figure 24: Combined input circuit for 11 A, 1 Vpp (with 120 termination) or TTL encoder signals. RS3/4 and CS1 serve as protection against ESD and transients.
IC-NQC
preliminary
Rev B1, Page 27/29
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
Basic circuit
Figure 25: Basic circuit for the evaluation of MR bridge sensors.
EVALUATION BOARD IC-NQC comes with a demo board for test purposes. Instructions are available separately.
DESIGN REVIEW: Function Notes
IC-NQC 1 No.
Function, Parameter/Code
Description and Application Notes Please refer to datasheet release A1.
Table 53: Notes on chip functions regarding IC-NQC chip release 1.
IC-NQC 2 No.
Function, Parameter/Code
Description and Application Notes
Table 54: Notes on chip functions regarding IC-NQC chip release 2.
IC-NQC
preliminary
Rev B1, Page 28/29
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
iC-Haus expressly reserves the right to change its products and/or specifications. An info letter gives details as to any amendments and additions made to the relevant current specifications on our internet website www.ichaus.de/infoletter; this letter is generated automatically and shall be sent to registered users by email. Copying - even as an excerpt - is only permitted with iC-Haus' approval in writing and precise reference to source. iC-Haus does not warrant the accuracy, completeness or timeliness of the specification and does not assume liability for any errors or omissions in these materials. The data specified is intended solely for the purpose of product description. No representations or warranties, either express or implied, of merchantability, fitness for a particular purpose or of any other nature are made hereunder with respect to information/specification or the products to which information refers and no guarantee with respect to compliance to the intended use is given. In particular, this also applies to the stated possible applications or areas of applications of the product. iC-Haus conveys no patent, copyright, mask work right or other trade mark right to this product. iC-Haus assumes no liability for any patent and/or other trade mark rights of a third party resulting from processing or handling of the product and/or any other use of the product. As a general rule our developments, IPs, principle circuitry and range of Integrated Circuits are suitable and specifically designed for appropriate use in technical applications, such as in devices, systems and any kind of technical equipment, in so far as they do not infringe existing patent rights. In principle the range of use is limitless in a technical sense and refers to the products listed in the inventory of goods compiled for the 2008 and following export trade statistics issued annually by the Bureau of Statistics in Wiesbaden, for example, or to any product in the product catalogue published for the 2007 and following exhibitions in Hanover (Hannover-Messe). We understand suitable application of our published designs to be state-of-the-art technology which can no longer be classed as inventive under the stipulations of patent law. Our explicit application notes are to be treated only as mere examples of the many possible and extremely advantageous uses our products can be put to.
IC-NQC
preliminary
Rev B1, Page 29/29
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
ORDERING INFORMATION
Type IC-NQC Evaluation Board
Package TSSOP20 4.4 mm
Order Designation IC-NQC TSSOP20 IC-NQC EVAL NQ6D
For technical support, information about prices and terms of delivery please contact: iC-Haus GmbH Am Kuemmerling 18 D-55294 Bodenheim GERMANY Tel.: +49 (61 35) 92 92-0 Fax: +49 (61 35) 92 92-192 Web: http://www.ichaus.com E-Mail: sales@ichaus.com
Appointed local distributors: http://www.ichaus.com/sales_partners

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